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1. general description the lpc1311/13/42/43 are arm cortex-m3 based microcontrollers for embedded applications featuring a high level of integration and low power consumption. the arm cortex-m3 is a next generation core that offers system enhancements such as enhanced debug features and a higher level of support block integration. the lpc1311/13/42/43 operate at cpu frequencies of up to 72 mhz. the arm cortex-m3 cpu incorporates a 3-stage pipeline and uses a harvard architecture with separate local instruction and data buses as well as a third bus for peripherals. the arm cortex-m3 cpu also includes an internal prefetch unit that supports speculative branching. the peripheral complement of the lpc1311/13/42/43 includes up to 32 kb of ?ash memory, up to 8 kb of data memory, usb device (lpc1342/43 only), one fast-mode plus i 2 c-bus interface, one uart, four general purpose timers, and up to 42 general purpose i/o pins. 2. features n arm cortex-m3 processor, running at frequencies of up to 72 mhz. n arm cortex-m3 built-in nested vectored interrupt controller (nvic). n 32 kb (lpc1343/13)/16 kb (lpc1342)/8 kb (lpc1311) on-chip ?ash programming memory. n 8 kb (lpc1343/13)/4 kb (lpc1342/11) sram. n in-system programming (isp) and in-application programming (iap) via on-chip bootloader software. n selectable boot-up: uart or usb (usb on lpc134x only). n serial interfaces: u usb 2.0 full-speed device controller with on-chip phy for device (lpc1342/43 only). u uart with fractional baud rate generation, modem, internal fifo, and rs-485/eia-485 support. u ssp controller with fifo and multi-protocol capabilities. u i 2 c-bus interface supporting full i 2 c-bus speci?cation and fast-mode plus with a data rate of 1 mbit/s with multiple address recognition and monitor mode. n other peripherals: lpc1311/13/42/43 32-bit arm cortex-m3 microcontroller; up to 32 kb ?ash and 8 kb sram; usb device rev. 01 11 december 2009 product data sheet
lpc1311_13_42_43_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 11 december 2009 2 of 53 nxp semiconductors lpc1311/13/42/43 32-bit arm cortex-m3 microcontroller u up to 42 general purpose i/o (gpio) pins with con?gurable pull-up/pull-down resistors. u four general purpose timers/counters with a total of four capture inputs and 13 match outputs. u programmable watchdog timer (wdt). u system tick timer. n serial wire debug and serial wire trace port. n high-current output driver (20 ma) on one pin. n high-current sink drivers (20 ma) on two i 2 c-bus pins in fast-mode plus. n integrated pmu (power management unit) to minimize power consumption during sleep, deep-sleep, and deep power-down modes. n three reduced power modes: sleep, deep-sleep, and deep power-down. n single 3.3 v power supply (2.0 v to 3.6 v). n 10-bit adc with input multiplexing among 8 pins. n gpio pins can be used as edge and level sensitive interrupt sources. n clock output function with divider that can re?ect the system oscillator clock, irc clock, cpu clock, or the watchdog clock. n processor wake-up from deep-sleep mode via a dedicated start logic using up to 40 of the functional pins. n brownout detect with four separate thresholds for interrupt and one threshold for forced reset. n power-on reset (por). n crystal oscillator with an operating range of 1 mhz to 25 mhz. n 12 mhz internal rc oscillator trimmed t o 1 % accuracy that can optionally be used as a system clock. n pll allows cpu operation up to the maximum cpu rate without the need for a high-frequency crystal. may be run from the main oscillator, the internal rc oscillator, or the watchdog oscillator. n code read protection (crp) with different security levels. n available as 48-pin lqfp package and 33-pin hvqfn package. 3. applications n emetering n lighting n industrial networking n alarm systems n white goods
lpc1311_13_42_43_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 11 december 2009 3 of 53 nxp semiconductors lpc1311/13/42/43 32-bit arm cortex-m3 microcontroller 4. ordering information 4.1 ordering options table 1. ordering information type number package name description version lpc1311fhn33 hvqfn33 hvqfn33: plastic thermal enhanced very thin quad ?at package; no leads; 33 terminals; body 7 x 7 x 0.85 mm n/a LPC1313fbd48 lqfp48 lqfp48: plastic low pro?le quad ?at package; 48 leads; bod y7x7x1.4mm so t313-2 LPC1313fhn33 hvqfn33 hvqfn33: plastic thermal enhanced very thin quad ?at package; no leads; 33 terminals; body 7 x 7 x 0.85 mm n/a lpc1342fhn33 hvqfn33 hvqfn33: plastic thermal enhanced very thin quad ?at package; no leads; 33 terminals; body 7 x 7 x 0.85 mm n/a lpc1343fbd48 lqfp48 lqfp48: plastic low pro?le quad ?at package; 48 leads; bod y7x7x1.4mm so t313-2 lpc1343fhn33 hvqfn33 hvqfn33: plastic thermal enhanced very thin quad ?at package; no leads; 33 terminals; body 7 x 7 x 0.85 mm n/a table 2. ordering options for lpc1311/13/42/43 type number flash total sram usb uart rs-485 i 2 c/ fast+ ssp adc channels pins package lpc1311fhn33 8 kb 4 kb - 1 1 1 8 33 hvqfn33 LPC1313fbd48 32 kb 8 kb - 1 1 1 8 48 lqfp48 LPC1313fhn33 32 kb 8 kb - 1 1 1 8 33 hvqfn33 lpc1342fhn33 16 kb 4 kb device 1 1 1 8 33 hvqfn33 lpc1343fbd48 32 kb 8 kb device 1 1 1 8 48 lqfp48 lpc1343fhn33 32 kb 8 kb device 1 1 1 8 33 hvqfn33
lpc1311_13_42_43_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 11 december 2009 4 of 53 nxp semiconductors lpc1311/13/42/43 32-bit arm cortex-m3 microcontroller 5. block diagram (1) lpc1342/43 only. (2) lqfp48 package only. fig 1. block diagram sram 4/8 kb arm cortex-m3 test/debug interface flash 8/16/32 kb usb device controller (1) i-code bus d-code bus system bus ahb to apb bridge high-speed gpio clock generation, power control, system functions xtalin xtalout reset clocks and controls swd usb phy (1) ssp 10-bit adc uart 32-bit counter/timer 0 i 2 c-bus wdt ioconfig lpc1311/13/42/43 slave 002aae722 slave slave slave slave rom slave ahb-lite bus gpio ports pio0/1/2/3 ct32b0_mat[3:0] ad[7:0] ct32b0_cap0 sda scl rxd txd dtr, dsr (2) , cts, dcd (2) , ri (2) , rts system control 32-bit counter/timer 1 ct32b1_mat[3:0] ct32b1_cap0 16-bit counter/timer 1 ct16b1_mat[1:0] ct16b1_cap0 16-bit counter/timer 0 ct16b0_mat[2:0] ct16b0_cap0 usb pins sck ssel miso mosi clkout irc por
lpc1311_13_42_43_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 11 december 2009 5 of 53 nxp semiconductors lpc1311/13/42/43 32-bit arm cortex-m3 microcontroller 6. pinning information 6.1 pinning fig 2. lpc1343 lqfp48 package lpc1343fbd48 pio2_6 pio3_0 pio2_0/dtr trst/pio1_2/ad3/ct32b1_mat1 reset/pio0_0 tdo/pio1_1/ad2/ct32b1_mat0 pio0_1/clkout/ct32b0_mat2/usb_ftoggle tms/pio1_0/ad1/ct32b1_cap0 v ssio tdi/pio0_11/ad0/ct32b0_mat3 xtalin pio2_11/sck xtalout pio1_10/ad6/ct16b1_mat1 v dd(io) swclk/pio0_10/sck/ct16b0_mat2 pio1_8/ct16b1_cap0 pio0_9/mosi/ct16b0_mat1/swo pio0_2/ssel/ct16b0_cap0 pio0_8/miso/ct16b0_mat0 pio2_7 pio2_2/dcd pio2_8 pio2_10 pio2_1/dsr pio3_3 pio0_3/usb_vbus pio1_7/txd/ct32b0_mat1 pio0_4/scl pio1_6/rxd/ct32b0_mat0 pio0_5/sda pio1_5/rts/ct32b0_cap0 pio1_9/ct16b1_mat0 v dd(3v3) pio2_4 pio3_2 usb_dm pio1_11/ad7 usb_dp v ss pio2_5 pio1_4/ad5/ct32b1_mat3/wakeup pio0_6/usb_connect/sck swdio/pio1_3/ad4/ct32b1_mat2 pio0_7/cts pio2_9 pio2_3/ri pio3_1 002aae505 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 48 47 46 45 44 43 42 41 40 39 38 37 24
lpc1311_13_42_43_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 11 december 2009 6 of 53 nxp semiconductors lpc1311/13/42/43 32-bit arm cortex-m3 microcontroller fig 3. lpc1342/43 hvqfn33 package 002aae516 lpc1342fhn33 lpc1343fhn33 transparent top view pio0_8/miso/ct16b0_mat0 pio1_8/ct16b1_cap0 pio0_2/ssel/ct16b0_cap0 pio0_9/mosi/ct16b0_mat1/swo v dd(io) swclk/pio0_10/sck/ct16b0_mat2 xtalout pio1_10/ad6/ct16b1_mat1 xtalin tdi/pio0_11/ad0/ct32b0_mat3 pio0_1/clkout/ct32b0_mat2/usb_ftoggle tms/pio1_0/ad1/ct32b1_cap0 reset/pio0_0 tdo/pio1_1/ad2/ct32b1_mat0 pio2_0/dtr trst/pio1_2/ad3/ct32b1_mat1 pio0_3/usb_vbus pio0_4/scl pio0_5/sda pio1_9/ct16b1_mat0 usb_dm usb_dp pio0_6/usb_connect/sck pio0_7/cts pio1_7/txd/ct32b0_mat1 pio1_6/rxd/ct32b0_mat0 pio1_5/rts/ct32b0_cap0 v dd(3v3) pio3_2 pio1_11/ad7 pio1_4/ad5/ct32b1_mat3/wakeup swdio/pio1_3/ad4/ct32b1_mat2 8 17 7 18 6 19 5 20 4 21 3 22 2 23 1 24 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 terminal 1 index area 33 v ss
lpc1311_13_42_43_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 11 december 2009 7 of 53 nxp semiconductors lpc1311/13/42/43 32-bit arm cortex-m3 microcontroller fig 4. LPC1313 lqfp48 package LPC1313fbd48 pio2_6 pio3_0 pio2_0/dtr trst/pio1_2/ad3/ct32b1_mat1 reset/pio0_0 tdo/pio1_1/ad2/ct32b1_mat0 pio0_1/clkout/ct32b0_mat2 tms/pio1_0/ad1/ct32b1_cap0 v ssio tdi/pio0_11/ad0/ct32b0_mat3 xtalin pio2_11/sck xtalout pio1_10/ad6/ct16b1_mat1 v dd(io) swclk/pio0_10/sck/ct16b0_mat2 pio1_8/ct16b1_cap0 pio0_9/mosi/ct16b0_mat1/swo pio0_2/ssel/ct16b0_cap0 pio0_8/miso/ct16b0_mat0 pio2_7 pio2_2/dcd pio2_8 pio2_10 pio2_1/dsr pio3_3 pio0_3 pio1_7/txd/ct32b0_mat1 pio0_4/scl pio1_6/rxd/ct32b0_mat0 pio0_5/sda pio1_5/rts/ct32b0_cap0 pio1_9/ct16b1_mat0 v dd(3v3) pio3_4 pio3_2 pio2_4 pio1_11/ad7 pio2_5 v ss pio3_5 pio1_4/ad5/ct32b1_mat3/wakeup pio0_6/sck swdio/pio1_3/ad4/ct32b1_mat2 pio0_7/cts pio2_9 pio2_3/ri pio3_1 002aae513 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 48 47 46 45 44 43 42 41 40 39 38 37 24
lpc1311_13_42_43_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 11 december 2009 8 of 53 nxp semiconductors lpc1311/13/42/43 32-bit arm cortex-m3 microcontroller 6.2 pin description fig 5. lpc1311/13 hvqfn33 package 002aae517 lpc1311fhn33 LPC1313fhn33 transparent top view pio0_8/miso/ct16b0_mat0 pio1_8/ct16b1_cap0 pio0_2/ssel/ct16b0_cap0 pio0_9/mosi/ct16b0_mat1/swo v dd(io) swclk/pio0_10/sck/ct16b0_mat2 xtalout pio1_10/ad6/ct16b1_mat1 xtalin tdi/pio0_11/ad0/ct32b0_mat3 pio0_1/clkout/ct32b0_mat2 tms/pio1_0/ad1/ct32b1_cap0 reset/pio0_0 tdo/pio1_1/ad2/ct32b1_mat0 pio2_0/dtr trst/pio1_2/ad3/ct32b1_mat1 pio0_3 pio0_4/scl pio0_5/sda pio1_9/ct16b1_mat0 pio3_4 pio3_5 pio0_6/sck pio0_7/cts pio1_7/txd/ct32b0_mat1 pio1_6/rxd/ct32b0_mat0 pio1_5/rts/ct32b0_cap0 v dd(3v3) pio3_2 pio1_11/ad7 pio1_4/ad5/ct32b1_mat3/wakeup swdio/pio1_3/ad4/ct32b1_mat2 8 17 7 18 6 19 5 20 4 21 3 22 2 23 1 24 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 terminal 1 index area 33 v ss table 3. LPC1313/43 lqfp48 pin description table symbol pin type description reset/pio0_0 3 i reset external reset input: a low on this pin resets the device, causing i/o ports and peripherals to take on their default states, and processor execution to begin at address 0. i/o pio0_0 general purpose digital input/output pin. pio0_1/clkout/ ct32b0_mat2/ usb_ftoggle 4 [1] i/o pio0_1 general purpose digital input/output pin. a low level on this pin during reset starts the isp command handler or the usb device enumeration (usb on lpc1343 only, see description of pio0_3). o clkout clockout pin. o ct32b0_mat2 match output 2 for 32-bit timer 0. o usb_ftoggle usb 1 ms start-of-frame signal (lpc1343 only). pio0_2/ssel/ ct16b0_cap0 10 [1] i/o pio0_2 general purpose digital input/output pin. o ssel slave select for ssp. i ct16b0_cap0 capture input 0 for 16-bit timer 0.
lpc1311_13_42_43_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 11 december 2009 9 of 53 nxp semiconductors lpc1311/13/42/43 32-bit arm cortex-m3 microcontroller pio0_3/usb_vbus 14 [1] i/o pio0_3 general purpose digital input/output pin. lpc1343 only: a low level on this pin during reset starts the isp command handler, a high level starts the usb device enumeration. i usb_vbus monitors the presence of usb bus power (lpc1343 only). pio0_4/scl 15 [2] i/o pio0_4 general purpose digital input/output pin. i/o scl i 2 c-bus clock input/output. high-current sink only if i 2 c fast-mode plus is selected in the i/o con?guration register. pio0_5/sda 16 [2] i/o pio0_5 general purpose digital input/output pin. i/o sda i 2 c-bus data input/output. high-current sink only if i 2 c fast-mode plus is selected in the i/o con?guration register. pio0_6/ usb_connect/ sck 22 [1] i/o pio0_6 general purpose digital input/output pin. o usb_connect signal used to switch an external 1.5 k w resistor under software control. used with the softconnect usb feature (lpc1343 only). i/o sck serial clock for ssp. pio0_7/ cts 23 [1] i/o pio0_7 general purpose digital input/output pin (high-current output driver). i cts clear to send input for uart. pio0_8/miso/ ct16b0_mat0 27 [1] i/o pio0_8 general purpose digital input/output pin. i/o miso master in slave out for ssp. o ct16b0_mat0 match output 0 for 16-bit timer 0. pio0_9/mosi/ ct16b0_mat1/ swo 28 [1] i/o pio0_9 general purpose digital input/output pin. i/o mosi master out slave in for ssp. o ct16b0_mat1 match output 1 for 16-bit timer 0. o swo serial wire trace output. swclk/pio0_10/ sck/ct16b0_mat2 29 [1] i swclk serial wire clock and test clock tck for jtag interface. i/o pio0_10 general purpose digital input/output pin. o sck serial clock for ssp. o ct16b0_mat2 match output 2 for 16-bit timer 0. tdi/pio0_11/ ad0/ct32b0_mat3 32 [3] i tdi test data in for jtag interface. i/o pio0_11 general purpose digital input/output pin. i ad0 a/d converter, input 0. o ct32b0_mat3 match output 3 for 32-bit timer 0. tms/pio1_0/ ad1/ct32b1_cap0 33 [3] i tms test mode select for jtag interface. i/o pio1_0 general purpose digital input/output pin. i ad1 a/d converter, input 1. i ct32b1_cap0 capture input 0 for 32-bit timer 1. tdo/pio1_1/ ad2/ct32b1_mat0 34 [3] o tdo test data out for jtag interface. i/o pio1_1 general purpose digital input/output pin. i ad2 a/d converter, input 2. o ct32b1_mat0 match output 0 for 32-bit timer 1. table 3. LPC1313/43 lqfp48 pin description table continued symbol pin type description
lpc1311_13_42_43_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 11 december 2009 10 of 53 nxp semiconductors lpc1311/13/42/43 32-bit arm cortex-m3 microcontroller trst/pio1_2/ ad3/ct32b1_mat1 35 [3] i trst test reset for jtag interface. i/o pio1_2 general purpose digital input/output pin. i ad3 a/d converter, input 3. o ct32b1_mat1 match output 1 for 32-bit timer 1. swdio/pio1_3/ad4/ ct32b1_mat2 39 [3] i/o swdio serial wire debug input/output. i/o pio1_3 general purpose digital input/output pin. i ad4 a/d converter, input 4. o ct32b1_mat2 match output 2 for 32-bit timer 1. pio1_4/ad5/ ct32b1_mat3/wakeup 40 [3] i/o pio1_4 general purpose digital input/output pin. i ad5 a/d converter, input 5. o ct32b1_mat3 match output 3 for 32-bit timer 1. i wakeup deep power-down mode wake-up pin. this pin must be pulled high externally to enter deep power-down mode and pulled low to exit deep power-down mode. pio1_5/ r ts/ ct32b0_cap0 45 [1] i/o pio1_5 general purpose digital input/output pin. o r ts request to send output for uart. i ct32b0_cap0 capture input 0 for 32-bit timer 0. pio1_6/rxd/ ct32b0_mat0 46 [1] i/o pio1_6 general purpose digital input/output pin. i rxd receiver input for uart. o ct32b0_mat0 match output 0 for 32-bit timer 0. pio1_7/txd/ ct32b0_mat1 47 [1] i/o pio1_7 general purpose digital input/output pin. o txd transmitter output for uart. o ct32b0_mat1 match output 1 for 32-bit timer 0. pio1_8/ct16b1_cap0 9 [1] i/o pio1_8 general purpose digital input/output pin. i ct16b1_cap0 capture input 0 for 16-bit timer 1. pio1_9/ct16b1_mat0 17 [1] i/o pio1_9 general purpose digital input/output pin. o ct16b1_mat0 match output 0 for 16-bit timer 1. pio1_10/ad6/ ct16b1_mat1 30 [3] i/o pio1_10 general purpose digital input/output pin. i ad6 a/d converter, input 6. o ct16b1_mat1 match output 1 for 16-bit timer 1. pio1_11/ad7 42 [3] i/o pio1_11 general purpose digital input/output pin. i ad7 a/d converter, input 7. pio2_0/ dtr 2 [1] i/o pio2_0 general purpose digital input/output pin. o dtr data terminal ready output for uart. pio2_1/ dsr 13 [1] i/o pio2_1 general purpose digital input/output pin. i dsr data set ready input for uart. pio2_2/ dcd 26 [1] i/o pio2_2 general purpose digital input/output pin. i dcd data carrier detect input for uart. pio2_3/ ri 38 [1] i/o pio2_3 general purpose digital input/output pin. i ri ring indicator input for uart. pio2_4 18 [1] i/o pio2_4 general purpose digital input/output pin (lpc1343 only). table 3. LPC1313/43 lqfp48 pin description table continued symbol pin type description
lpc1311_13_42_43_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 11 december 2009 11 of 53 nxp semiconductors lpc1311/13/42/43 32-bit arm cortex-m3 microcontroller [1] 5 v tolerant pad providing digital i/o functions with con?gurable pull-up/pull-down resistors and con?gurable hysteresis. [2] i 2 c-bus pads compliant with the i 2 c-bus speci?cation for i 2 c standard mode and i 2 c fast-mode plus. [3] 5 v tolerant pad providing digital i/o functions with con?gurable pull-up/pull-down resistors, con?gurable hysteresis, and a nalog input. when con?gured as a adc input, digital section of the pad is disabled and the pin is not 5 v tolerant. [4] pad provides usb functions. it is designed in accordance with the usb speci?cation, revision 2.0 (full-speed and low-speed m ode only). [5] tie together v dd(3v3) and v dd(io) externally. if separate supplies are used for v dd(3v3) and v dd(io) , ensure that the voltage difference between both supplies is smaller than or equal to 0.5 v. [6] when the system oscillator is not used, connect xtalin and xtalout as follows: xtalin can be left ?oating or can be grounded (grounding is preferred to reduce susceptibility to noise). xtalout should be left ?oating. pio2_4 19 [1] i/o pio2_4 general purpose digital input/output pin (LPC1313 only). pio2_5 21 [1] i/o pio2_5 general purpose digital input/output pin (lpc1343 only). pio2_5 20 [1] i/o pio2_5 general purpose digital input/output pin (LPC1313 only). pio2_6 1 [1] i/o pio2_6 general purpose digital input/output pin. pio2_7 11 [1] i/o pio2_7 general purpose digital input/output pin. pio2_8 12 [1] i/o pio2_8 general purpose digital input/output pin. pio2_9 24 [1] i/o pio2_9 general purpose digital input/output pin. pio2_10 25 [1] i/o pio2_10 general purpose digital input/output pin. pio2_11/sck 31 [1] i/o pio2_11 general purpose digital input/output pin. i/o sck serial clock for ssp. pio3_0 36 [1] i/o pio3_0 general purpose digital input/output pin. pio3_1 37 [1] i/o pio3_1 general purpose digital input/output pin. pio3_2 43 [1] i/o pio3_2 general purpose digital input/output pin. pio3_3 48 [1] i/o pio3_3 general purpose digital input/output pin. pio3_4 18 [1] i/o pio3_4 general purpose digital input/output pin (LPC1313 only). pio3_5 21 [1] i/o pio3_5 general purpose digital input/output pin (LPC1313 only). usb_dm 19 [4] i/o usb_dm usb bidirectional d - line (lpc1343 only). usb_dp 20 [4] i/o usb_dp usb bidirectional d+ line (lpc1343 only). v dd(io) 8 [5] i 3.3 v input/output supply voltage. v dd(3v3) 44 [5] i 3.3 v supply voltage to the internal regulator and the adc. also used as the adc reference voltage. v ssio 5 i ground. xtalin 6 [6] i input to the oscillator circuit and internal clock generator circuits. input voltage must not exceed 1.8 v. xtalout 7 [6] o output from the oscillator ampli?er. v ss 41 i ground. table 3. LPC1313/43 lqfp48 pin description table continued symbol pin type description
lpc1311_13_42_43_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 11 december 2009 12 of 53 nxp semiconductors lpc1311/13/42/43 32-bit arm cortex-m3 microcontroller table 4. lpc1311/13/42/43 hvqfn33 pin description table symbol pin type description reset/pio0_0 2 i reset external reset input: a low on this pin resets the device, causing i/o ports and peripherals to take on their default states, and processor execution to begin at address 0. i/o pio0_0 general purpose digital input/output pin. pio0_1/clkout/ ct32b0_mat2/ usb_ftoggle 3 [1] i/o pio0_1 general purpose digital input/output pin. a low level on this pin during reset starts the isp command handler or the usb device enumeration (usb on lpc1342/43 only, see description of pio0_3). o clkout clock out pin. o ct32b0_mat2 match output 2 for 32-bit timer 0. o usb_ftoggle usb 1 ms start-of-frame signal (lpc1342/43 only). pio0_2/ssel/ ct16b0_cap0 8 [1] i/o pio0_2 general purpose digital input/output pin. o ssel slave select for ssp. i ct16b0_cap0 capture input 0 for 16-bit timer 0. pio0_3/usb_vbus 9 [1] i/o pio0_3 general purpose digital input/output pin. lpc1342/43 only: a low level on this pin during reset starts the isp command handler, a high level starts the usb device enumeration. i usb_vbus monitors the presence of usb bus power (lpc1342/43 only). pio0_4/scl 10 [2] i/o pio0_4 general purpose digital input/output pin. i/o scl i 2 c-bus clock input/output. high-current sink only if i 2 c fast-mode plus is selected in the i/o con?guration register. pio0_5/sda 11 [2] i/o pio0_5 general purpose digital input/output pin. i/o sda i 2 c-bus data input/output. high-current sink only if i 2 c fast-mode plus is selected in the i/o con?guration register. pio0_6/ usb_connect/ sck 15 [1] i/o pio0_6 general purpose digital input/output pin. o usb_connect signal used to switch an external 1.5 k w resistor under software control. used with the softconnect usb feature (lpc1342/43 only). i/o sck serial clock for ssp. pio0_7/ cts 16 [1] i/o pio0_7 general purpose digital input/output pin (high-current output driver). i cts clear to send input for uart. pio0_8/miso/ ct16b0_mat0 17 [1] i/o pio0_8 general purpose digital input/output pin. i/o miso master in slave out for ssp. o ct16b0_mat0 match output 0 for 16-bit timer 0. pio0_9/mosi/ ct16b0_mat1/ swo 18 [1] i/o pio0_9 general purpose digital input/output pin. i/o mosi master out slave in for ssp. o ct16b0_mat1 match output 1 for 16-bit timer 0. o swo serial wire trace output. swclk/pio0_10/sck/ ct16b0_mat2 19 [1] i swclk serial wire clock and test clock tck for jtag interface. i/o pio0_10 general purpose digital input/output pin. o sck serial clock for ssp. o ct16b0_mat2 match output 2 for 16-bit timer 0.
lpc1311_13_42_43_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 11 december 2009 13 of 53 nxp semiconductors lpc1311/13/42/43 32-bit arm cortex-m3 microcontroller tdi/pio0_11/ad0/ ct32b0_mat3 21 [3] i tdi test data in for jtag interface. i/o pio0_11 general purpose digital input/output pin. i ad0 a/d converter, input 0. o ct32b0_mat3 match output 3 for 32-bit timer 0. tms/pio1_0/ad1/ ct32b1_cap0 22 [3] i tms test mode select for jtag interface. i/o pio1_0 general purpose digital input/output pin. i ad1 a/d converter, input 1. i ct32b1_cap0 capture input 0 for 32-bit timer 1. tdo/pio1_1/ad2/ ct32b1_mat0 23 [3] o tdo test data out for jtag interface. i/o pio1_1 general purpose digital input/output pin. i ad2 a/d converter, input 2. o ct32b1_mat0 match output 0 for 32-bit timer 1. trst/pio1_2/ad3/ ct32b1_mat1 24 [3] i trst test reset for jtag interface. i/o pio1_2 general purpose digital input/output pin. i ad3 a/d converter, input 3. o ct32b1_mat1 match output 1 for 32-bit timer 1. swdio/pio1_3/ad4/ ct32b1_mat2 25 [3] i/o swdio serial wire debug input/output. i/o pio1_3 general purpose digital input/output pin. i ad4 a/d converter, input 4. o ct32b1_mat2 match output 2 for 32-bit timer 1. pio1_4/ad5/ ct32b1_mat3/wakeup 26 [3] i/o pio1_4 general purpose digital input/output pin. i ad5 a/d converter, input 5. o ct32b1_mat3 match output 3 for 32-bit timer 1. i wakeup deep power-down mode wake-up pin. this pin must be pulled high externally to enter deep power-down mode and pulled low to exit deep power-down mode. pio1_5/ r ts/ ct32b0_cap0 30 [1] i/o pio1_5 general purpose digital input/output pin. o r ts request to send output for uart. i ct32b0_cap0 capture input 0 for 32-bit timer 0. pio1_6/rxd/ ct32b0_mat0 31 [1] i/o pio1_6 general purpose digital input/output pin. i rxd receiver input for uart. o ct32b0_mat0 match output 0 for 32-bit timer 0. pio1_7/txd/ ct32b0_mat1 32 [1] i/o pio1_7 general purpose digital input/output pin. o txd transmitter output for uart. o ct32b0_mat1 match output 1 for 32-bit timer 0. pio1_8/ct16b1_cap0 7 [1] i/o pio1_8 general purpose digital input/output pin. i ct16b1_cap0 capture input 0 for 16-bit timer 1. pio1_9/ct16b1_mat0 12 [1] i/o pio1_9 general purpose digital input/output pin. o ct16b1_mat0 match output 0 for 16-bit timer 1. table 4. lpc1311/13/42/43 hvqfn33 pin description table continued symbol pin type description
lpc1311_13_42_43_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 11 december 2009 14 of 53 nxp semiconductors lpc1311/13/42/43 32-bit arm cortex-m3 microcontroller [1] 5 v tolerant pad providing digital i/o functions with con?gurable pull-up/pull-down resistors and con?gurable hysteresis. [2] i 2 c-bus pads compliant with the i 2 c-bus speci?cation for i 2 c standard mode and i 2 c fast-mode plus. [3] 5 v tolerant pad providing digital i/o functions with con?gurable pull-up/pull-down resistors, con?gurable hysteresis, and a nalog input. when con?gured as a adc input, digital section of the pad is disabled, and the pin is not 5 v tolerant. [4] pad provides usb functions. it is designed in accordance with the usb speci?cation, revision 2.0 (full-speed and low-speed m ode only). [5] tie together v dd(3v3) and v dd(io) externally. if separate supplies are used for v dd(3v3) and v dd(io) , ensure that the voltage difference between both supplies is smaller than or equal to 0.5 v. [6] when the system oscillator is not used, connect xtalin and xtalout as follows: xtalin can be left ?oating or can be grounded (grounding is preferred to reduce susceptibility to noise). xtalout should be left ?oating. 7. functional description 7.1 architectural overview the arm cortex-m3 includes three ahb-lite buses: the system bus, the i-code bus, and the d-code bus (see figure 1 ). the i-code and d-code core buses are faster than the system bus and are used similarly to tcm interfaces: one bus dedicated for instruction fetch (i-code) and one bus for data access (d-code). the use of two core buses allows for simultaneous operations if concurrent operations target different devices. 7.2 arm cortex-m3 processor the arm cortex-m3 is a general purpose, 32-bit microprocessor, which offers high performance and very low power consumption. the arm cortex-m3 offers many new features, including a thumb-2 instruction set, low interrupt latency, hardware divide, pio1_10/ad6/ ct16b1_mat1 20 [3] i/o pio1_10 general purpose digital input/output pin. i ad6 a/d converter, input 6. o ct16b1_mat1 match output 1 for 16-bit timer 1. pio1_11/ad7 27 [3] i/o pio1_11 general purpose digital input/output pin. i ad7 a/d converter, input 7. pio2_0/ dtr 1 [1] i/o pio2_0 general purpose digital input/output pin. o dtr data terminal ready output for uart. pio3_2 28 [1] i/o pio3_2 general purpose digital input/output pin. pio3_4 13 [1] i/o pio3_4 general purpose digital input/output pin (lpc1311/13 only). pio3_5 14 [1] i/o pio3_5 general purpose digital input/output pin (lpc1311/13 only). usb_dm 13 [4] i/o usb_dm usb bidirectional d - line (lpc1342/43 only). usb_dp 14 [4] i/o usb_dp usb bidirectional d+ line (lpc1342/43 only). v dd(io) 6 [5] i 3.3 v input/output supply voltage. v dd(3v3) 29 [5] i 3.3 v supply voltage to the internal dc-dc converter and the adc. also used as the adc reference voltage. xtalin 4 [6] i input to the oscillator circuit and internal clock generator circuits. input voltage must not exceed 1.8 v. xtalout 5 [6] o output from the oscillator ampli?er. v ss 33 - thermal pad. connect to ground. table 4. lpc1311/13/42/43 hvqfn33 pin description table continued symbol pin type description
lpc1311_13_42_43_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 11 december 2009 15 of 53 nxp semiconductors lpc1311/13/42/43 32-bit arm cortex-m3 microcontroller interruptible/continuable multiple load and store instructions, automatic state save and restore for interrupts, tightly integrated interrupt controller, and multiple core buses capable of simultaneous accesses. pipeline techniques are employed so that all parts of the processing and memory systems can operate continuously. typically, while one instruction is being executed, its successor is being decoded, and a third instruction is being fetched from memory. the arm cortex-m3 processor is described in detail in the cortex-m3 technical reference manual which is available on the of?cial arm website. 7.3 on-chip ?ash program memory the lpc1311/13/42/43 contain 32 kb (LPC1313 and lpc1343), 16 kb (lpc1342), or 8 kb (lpc1311) of on-chip ?ash memory. 7.4 on-chip sram the lpc1311/13/42/43 contain a total of 8 kb (lpc1343 and LPC1313) or 4 kb (lpc1342 and lpc1311) on-chip static ram memory. 7.5 memory map the lpc134x incorporates several distinct memory regions, shown in the following ?gures. figure 6 shows the overall map of the entire address space from the user program viewpoint following reset. the interrupt vector area supports address remapping. the ahb peripheral area is 2 mb in size and is divided to allow for up to 128 peripherals. the apb peripheral area is 1 mb in size and is divided to allow for up to 64 peripherals. each peripheral of either type is allocated 16 kb of space. this allows simplifying the address decoding for each peripheral.
lpc1311_13_42_43_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 11 december 2009 16 of 53 nxp semiconductors lpc1311/13/42/43 32-bit arm cortex-m3 microcontroller 7.6 nested vectored interrupt controller (nvic) the nested vectored interrupt controller (nvic) is an integral part of the cortex-m3. the tight coupling to the cpu allows for low interrupt latency and ef?cient processing of late arriving interrupts. 7.6.1 features ? controls system exceptions and peripheral interrupts. ? on the lpc1311/13/42/43, the nvic supports 16 vectored interrupts. in addition, up to 40 of the individual gpio inputs are nvic-vector capable. fig 6. lpc1311/13/42/43 memory map 0x5000 0000 0x5001 0000 0x5002 0000 0x5020 0000 ahb peripherals 127- 4 reserved gpio pio1 1 0x5003 0000 0x5004 0000 gpio pio2 gpio pio3 2 3 gpio pio0 0 apb peripherals 0x4000 4000 0x4000 8000 0x4000 c000 0x4001 0000 0x4001 8000 0x4002 0000 0x4002 8000 0x4003 8000 0x4003 c000 0x4004 0000 0x4004 4000 0x4004 8000 0x4004 c000 0x4008 0000 0x4002 4000 0x4001 c000 0x4001 4000 0x4000 0000 wdt 32-bit counter/timer 0 32-bit counter/timer 1 adc uart pmu i 2 c-bus 10 - 13 reserved reserved 31 - 19 reserved 0 1 2 3 4 5 6 7 8 9 16 15 14 17 18 reserved reserved reserved 0x0000 0000 0 gb 0.5 gb 4 gb 1 gb 0x0000 4000 0x0000 2000 0x1000 2000 0x1000 1000 0x1fff 0000 0x1fff 4000 0x2200 0000 0x2000 0000 0x2400 0000 0x4000 0000 0x4008 0000 0x5000 0000 0x5020 0000 0xffff ffff reserved reserved reserved reserved apb peripherals ahb peripherals ahb sram bit-band alias addressing 8 kb sram (LPC1313/1343) 0x1000 0000 4 kb sram (lpc1311/1342) lpc1311/13/42/43 16 kb on-chip flash (lpc1342) 8 kb on-chip flash (lpc1311) 0x0000 8000 32 kb on-chip flash (LPC1313/43) 16 kb boot rom 0x0000 0000 0x0000 0200 active interrupt vectors + 512 byte i-code/d-code memory space 002aae723 ssp 16-bit counter/timer 1 16-bit counter/timer 0 usb (lpc1342/43 only) ioconfig system control reserved
lpc1311_13_42_43_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 11 december 2009 17 of 53 nxp semiconductors lpc1311/13/42/43 32-bit arm cortex-m3 microcontroller ? 8 programmable interrupt priority levels, with hardware priority level masking ? relocatable vector table. ? software interrupt generation. 7.6.2 interrupt sources each peripheral device has one interrupt line connected to the nvic but may have several interrupt ?ags. individual interrupt ?ags may also represent more than one interrupt source. any gpio pin (total of up to 42 pins) regardless of the selected function, can be programmed to generate an interrupt on a level, or rising edge or falling edge, or both. 7.7 ioconfig block the ioconfig block allows selected pins of the microcontroller to have more than one function. con?guration registers control the multiplexers to allow connection between the pin and the on-chip peripherals. peripherals should be connected to the appropriate pins prior to being activated and prior to any related interrupt(s) being enabled. activity of any enabled peripheral function that is not mapped to a related pin should be considered unde?ned. 7.8 fast general purpose parallel i/o device pins that are not connected to a speci?c peripheral function are controlled by the gpio registers. pins may be dynamically con?gured as inputs or outputs. separate registers allow setting or clearing any number of outputs simultaneously. the value of the output register may be read back as well as the current state of the port pins. lpc1311/13/42/43 use accelerated gpio functions: ? gpio registers are a dedicated ahb peripheral and are accessed through the ahb so that the fastest possible i/o timing can be achieved. ? entire port value can be written in one instruction. additionally, any gpio pin (total of up to 42 pins) providing a digital function can be programmed to generate an interrupt on a level, a rising or falling edge, or both. 7.8.1 features ? bit level set and clear registers allow a single instruction to set or clear any number of bits in one port. ? direction control of individual bits. ? all i/o default to inputs with pull-up resistors enabled after reset. ? pull-up/pull-down resistor con?guration can be programmed through the ioconfig block for each gpio pin.
lpc1311_13_42_43_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 11 december 2009 18 of 53 nxp semiconductors lpc1311/13/42/43 32-bit arm cortex-m3 microcontroller 7.9 usb interface (lpc1342/43 only) the universal serial bus (usb) is a 4-wire bus that supports communication between a host and one or more (up to 127) peripherals. the host controller allocates the usb bandwidth to attached devices through a token-based protocol. the bus supports hot-plugging and dynamic con?guration of the devices. all transactions are initiated by the host controller. the lpc1342/43 usb interface is a device controller with on-chip phy for device functions. 7.9.1 full-speed usb device controller the device controller enables 12 mbit/s data exchange with a usb host controller. it consists of a register interface, serial interface engine, and endpoint buffer memory. the serial interface engine decodes the usb data stream and writes data to the appropriate endpoint buffer. the status of a completed usb transfer or error condition is indicated via status registers. an interrupt is also generated if enabled. 7.9.1.1 features ? fully compliant with usb 2.0 speci?cation (full speed) . ? supports 10 physical (5 logical) endpoints with up to 64 bytes buffer ram per endpoint (see t ab le 5 ). ? supports control, bulk, isochronous, and interrupt endpoints. ? supports softconnect feature. ? double buffer implementation for bulk and isochronous endpoints. 7.10 uart the lpc1311/13/42/43 contains one uart. support for rs-485/9-bit mode allows both software address detection and automatic address detection using 9-bit mode. the uart includes a fractional baud rate generator. standard baud rates such as 115200 bd can be achieved with any crystal frequency above 2 mhz. table 5. usb device endpoint con?guration logical endpoint physical endpoint endpoint type direction packet size (byte) double buffer 0 0 control out 64 no 0 1 control in 64 no 1 2 interrupt/bulk out 64 no 1 3 interrupt/bulk in 64 no 2 4 interrupt/bulk out 64 no 2 5 interrupt/bulk in 64 no 3 6 interrupt/bulk out 64 yes 3 7 interrupt/bulk in 64 yes 4 8 isochronous out 512 yes 4 9 isochronous in 512 yes
lpc1311_13_42_43_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 11 december 2009 19 of 53 nxp semiconductors lpc1311/13/42/43 32-bit arm cortex-m3 microcontroller 7.10.1 features ? 16-byte receive and transmit fifos. ? register locations conform to 16c550 industry standard. ? receiver fifo trigger points at 1 b, 4 b, 8 b, and 14 b. ? built-in fractional baud rate generator covering wide range of baud rates without a need for external crystals of particular values. ? fractional divider for baud rate control, auto baud capabilities and fifo control mechanism that enables software ?ow control implementation. ? support for rs-485/9-bit mode. ? support for modem control. 7.11 ssp serial i/o controller the lpc1311/13/42/43 contain one ssp controller. the ssp controller is capable of operation on a ssp, 4-wire ssi, or microwire bus. it can interact with multiple masters and slaves on the bus. only a single master and a single slave can communicate on the bus during a given data transfer. the ssp supports full duplex transfers, with frames of 4 bits to 16 bits of data ?owing from the master to the slave and from the slave to the master. in practice, often only one of these data ?ows carries meaningful data. 7.11.1 features ? compatible with motorola spi, 4-wire texas instruments ssi, and national semiconductor microwire buses ? synchronous serial communication ? master or slave operation ? 8-frame fifos for both transmit and receive ? 4-bit to 16-bit frame 7.12 i 2 c-bus serial i/o controller the lpc1311/13/42/43 contain one i 2 c-bus controller. the i 2 c-bus is bidirectional for inter-ic control using only two wires: a serial clock line (scl) and a serial data line (sda). each device is recognized by a unique address and can operate as either a receiver-only device (e.g., an lcd driver) or a transmitter with the capability to both receive and send information (such as memory). transmitters and/or receivers can operate in either master or slave mode, depending on whether the chip has to initiate a data transfer or is only addressed. the i 2 c is a multi-master bus and can be controlled by more than one bus master connected to it. 7.12.1 features ? the i 2 c-bus interface is a standard i 2 c-bus compliant interface with open-drain pins. the i 2 c-bus interface also supports fast-mode plus with bit rates up to 1 mbit/s. ? easy to con?gure as master, slave, or master/slave. ? programmable clocks allow versatile rate control. ? bidirectional data transfer between masters and slaves.
lpc1311_13_42_43_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 11 december 2009 20 of 53 nxp semiconductors lpc1311/13/42/43 32-bit arm cortex-m3 microcontroller ? multi-master bus (no central master). ? arbitration between simultaneously transmitting masters without corruption of serial data on the bus. ? serial clock synchronization allows devices with different bit rates to communicate via one serial bus. ? serial clock synchronization can be used as a handshake mechanism to suspend and resume serial transfer. ? the i 2 c-bus can be used for test and diagnostic purposes. ? the i 2 c-bus controller supports multiple address recognition and a bus monitor mode. 7.13 10-bit adc the lpc1311/13/42/43 contains one adc. it is a single 10-bit successive approximation adc with eight channels. 7.13.1 features ? 10-bit successive approximation adc. ? input multiplexing among 8 pins. ? power-down mode. ? measurement range 0 v to v dd(3v3) . ? 10-bit conversion time 3 2.44 m s. ? burst conversion mode for single or multiple inputs. ? optional conversion on transition of input pin or timer match signal. ? individual result registers for each adc channel to reduce interrupt overhead. 7.14 general purpose external event counters/timers the lpc1311/13/42/43 includes two 32-bit counter/timers and two 16-bit counter/timers. the counter/timer is designed to count cycles of the system derived clock. it can optionally generate interrupts or perform other actions at speci?ed timer values, based on four match registers. each counter/timer also includes one capture input to trap the timer value when an input signal transitions, optionally generating an interrupt. 7.14.1 features ? a 32-bit/16-bit timer/counter with a programmable 32-bit/16-bit prescaler. ? counter or timer operation. ? one capture channel per timer, that can take a snapshot of the timer value when an input signal transitions. a capture event may also generate an interrupt. ? four match registers per timer that allow: C continuous operation with optional interrupt generation on match. C stop timer on match with optional interrupt generation. C reset timer on match with optional interrupt generation. ? up to four external outputs corresponding to match registers, with the following capabilities:
lpc1311_13_42_43_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 11 december 2009 21 of 53 nxp semiconductors lpc1311/13/42/43 32-bit arm cortex-m3 microcontroller C set low on match. C set high on match. C toggle on match. C do nothing on match. 7.15 system tick timer the arm cortex-m3 includes a system tick timer (systick) that is intended to generate a dedicated systick exception, normally set to a 10 ms interval. 7.16 watchdog timer the purpose of the watchdog is to reset the microcontroller within a reasonable amount of time if it enters an erroneous state. when enabled, the watchdog will generate a system reset if the user program fails to feed (or reload) the watchdog within a predetermined amount of time. 7.16.1 features ? internally resets chip if not periodically reloaded. ? debug mode. ? enabled by software but requires a hardware reset or a watchdog reset/interrupt to be disabled. ? incorrect/incomplete feed sequence causes reset/interrupt if enabled. ? flag to indicate watchdog reset. ? programmable 32-bit timer with internal prescaler. ? selectable time period from (t cy(wdclk) 256 4) to (t cy(wdclk) 2 32 4) in multiples of t cy(wdclk) 4. ? the watchdog clock (wdclk) source can be selected from the internal rc oscillator (irc), the watchdog oscillator, or the main clock. this gives a wide range of potential timing choices of watchdog operation under different power reduction conditions. it also provides the ability to run the wdt from an entirely internal source that is not dependent on an external crystal and its associated components and wiring for increased reliability. 7.17 clocking and power control 7.17.1 crystal oscillators the lpc1311/13/42/43 include three independent oscillators. these are the system oscillator, the internal rc oscillator (irc), and the watchdog oscillator. each oscillator can be used for more than one purpose as required in a particular application. following reset, the lpc1311/13/42/43 will operate from the internal rc oscillator until switched by software. this allows systems to operate without any external crystal and the bootloader code to operate at a known frequency. see figure 7 for an overview of the lpc1311/13/42/43 clock generation.
lpc1311_13_42_43_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 11 december 2009 22 of 53 nxp semiconductors lpc1311/13/42/43 32-bit arm cortex-m3 microcontroller 7.17.1.1 internal rc oscillator the irc may be used as the clock source for the wdt, and/or as the clock that drives the system pll and subsequently the cpu. the nominal irc frequency is 12 mhz. the irc is trimmed to 1 % accuracy over the entire voltage and temperature range. the usb clock is available on lpc1342/43 only. fig 7. lpc1311/13/42/43 clocking generation block diagram system pll irc oscillator system oscillator system oscillator watchdog oscilllator watchdog oscillator irc oscillator watchdog oscillator usb pll mainclksel (main clock select) syspllclksel (system pll clock select) usbpllclksel (usb clock select) system clock divider ahbclkctrl (ahb clock enable) ahb clock 0 (system) ahb clock 1 (rom) ahb clock 16 (ioconfig) ahbclkctrl ahbclkctrl ssp peripheral clock divider ssp uart peripheral clock divider uart systick timer clock divider wdt clock divider systick timer arm trace clock divider arm trace clock wdt wdtuen (wdt clock update enable) usb 48 mhz clock divider usb usbuen (usb clock update enable) watchdog oscillator irc oscillator system oscillator clkout pin clock divider clkout pin clkoutuen (clkout update enable) 002aae859 main clock system clock irc oscillator ahb clocks 2 to 15 (memories and peripherals) 14
lpc1311_13_42_43_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 11 december 2009 23 of 53 nxp semiconductors lpc1311/13/42/43 32-bit arm cortex-m3 microcontroller upon power-up, any chip reset, or wake-up from deep power-down mode, the lpc1311/13/42/43 use the irc as the clock source. software may later switch to one of the other available clock sources. 7.17.1.2 system oscillator the system oscillator can be used as the clock source for the cpu, with or without using the pll. on the lpc134x, the system oscillator must be used to provide the clock source to usb. the system oscillator operates at frequencies of 1 mhz to 25 mhz. this frequency can be boosted to a higher frequency, up to the maximum cpu operating frequency, by the system pll. 7.17.2 system pll and usb pll the lpc134x contain a system pll and a dedicated pll for generating the 48 mhz usb clock. the lpc131x contain the system pll only. the system and usb plls are identical. the pll accepts an input clock frequency in the range of 10 mhz to 25 mhz. the input frequency is multiplied up to a high frequency with a current controlled oscillator (cco). the multiplier can be an integer value from 1 to 32. the cco operates in the range of 156 mhz to 320 mhz, so there is an additional divider in the loop to keep the cco within its frequency range while the pll is providing the desired output frequency. the output divider may be set to divide by 2, 4, 8, or 16 to produce the output clock. since the minimum output divider value is 2, it is insured that the pll output has a 50 % duty cycle. the pll is turned off and bypassed following a chip reset and may be enabled by software. the program must con?gure and activate the pll, wait for the pll to lock, and then connect to the pll as a clock source. the pll settling time is 100 m s. 7.17.3 clock output the lpc1311/13/42/43 features a clock output function that routes the irc oscillator, the system oscillator, the watchdog oscillator, or the main clock to an output pin. 7.17.4 wake-up process the lpc1311/13/42/43 begin operation at power-up and when awakened from deep power-down mode by using the 12 mhz irc oscillator as the clock source. this allows chip operation to resume quickly. if the main oscillator or the pll is needed by the application, software will need to enable these features and wait for them to stabilize before they are used as a clock source. 7.17.5 power control the lpc1311/13/42/43 support a variety of power control features. there are three special modes of processor power reduction: sleep mode, deep-sleep mode, and deep power-down mode. the cpu clock rate may also be controlled as needed by changing clock sources, recon?guring pll values, and/or altering the cpu clock divider value. this allows a trade-off of power versus processing speed based on application requirements. in addition, a register is provided for shutting down the clocks to individual on-chip peripherals, allowing ?ne tuning of power consumption by eliminating all dynamic power use in any peripherals that are not required for the application. selected peripherals have their own clock divider which provides even better power control.
lpc1311_13_42_43_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 11 december 2009 24 of 53 nxp semiconductors lpc1311/13/42/43 32-bit arm cortex-m3 microcontroller 7.17.5.1 sleep mode when sleep mode is entered, the clock to the core is stopped. resumption from the sleep mode does not need any special sequence but re-enabling the clock to the arm core. in sleep mode, execution of instructions is suspended until either a reset or interrupt occurs. peripheral functions continue operation during sleep mode and may generate interrupts to cause the processor to resume execution. sleep mode eliminates dynamic power used by the processor itself, memory systems and related controllers, and internal buses. 7.17.5.2 deep-sleep mode in deep-sleep mode, the chip is in sleep mode, and in addition analog blocks are shut down for increased power savings. the user can con?gure the deep-sleep mode to a large extend, selecting any of the oscillators, any of the plls, the usb phy (lpc134x only), bod, the adc, and the ?ash to be shut down or remain powered during deep-sleep mode. the user can also select which of the oscillators and analog blocks will be powered up after the chip exits from deep-sleep mode. the gpio pins (up to 40 pins total) serve as external wake-up pins to a dedicated start logic to wake up the chip from deep-sleep mode. the timing of the wake-up process from deep-sleep mode depends on which blocks are selected to be powered down during deep-sleep. for lowest power consumption, the clock source should be switched to irc before entering deep-sleep mode, all oscillators and plls should be turned off during deep-sleep, and the irc should be selected as clock source when the chip wakes up from deep-sleep. the irc can be switched on and off glitch-free and provides a clean clock signal after start-up. if power consumption is not a concern, any of the oscillators and/or plls can be left running in deep-sleep mode to obtain short wake-up times when waking up from deep-sleep. 7.17.5.3 deep power-down mode in deep power-down mode, power is shut off to the entire chip with the exception of the wakeup pin. the lpc1311/13/42/43 can wake up from deep power-down mode via the wakeup pin. 7.18 system control 7.18.1 reset reset has four sources on the lpc1311/13/42/43: the reset pin, the watchdog reset, power-on reset (por), and the brown-out detection (bod) circuit. the reset pin is a schmitt trigger input pin. assertion of chip reset by any source, once the operating voltage attains a usable level, starts the irc and initializes the ?ash controller. when the internal reset is removed, the processor begins executing at address 0, which is initially the reset vector mapped from the boot block. at that point, all of the processor and peripheral registers have been initialized to predetermined values.
lpc1311_13_42_43_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 11 december 2009 25 of 53 nxp semiconductors lpc1311/13/42/43 32-bit arm cortex-m3 microcontroller 7.18.2 brownout detection the lpc1311/13/42/43 includes four levels for monitoring the voltage on the v dd(3v3) pin. if this voltage falls below one of the four selected levels, the bod asserts an interrupt signal to the nvic. this signal can be enabled for interrupt in the interrupt enable register in the nvic in order to cause a cpu interrupt; if not, software can monitor the signal by reading a dedicated status register. an additional threshold level can be selected to cause a forced reset of the chip. 7.18.3 code security (code read protection - crp) this feature of the lpc1311/13/42/43 allows user to enable different levels of security in the system so that access to the on-chip ?ash and use of the jtag and isp can be restricted. when needed, crp is invoked by programming a speci?c pattern into a dedicated ?ash location. iap commands are not affected by the crp. there are three levels of code read protection: 1. crp1 disables access to chip via the jtag and allows partial ?ash update (excluding ?ash sector 0) using a limited set of the isp commands. this mode is useful when crp is required and ?ash ?eld updates are needed but all sectors can not be erased. 2. crp2 disables access to chip via the jtag and only allows full ?ash erase and update using a reduced set of the isp commands. 3. running an application with level crp3 selected fully disables any access to chip via the jtag pins and the isp. this mode effectively disables isp override using pio0_1 pin, too. it is up to the users application to provide (if needed) ?ash update mechanism using iap calls or call reinvoke isp command to enable ?ash update via uart0. in addition to the three crp levels, sampling of pin pio0_1 for valid user code can be disabled. for details see the lpc13xx user manual . 7.18.4 boot loader the boot loader controls initial operation after reset and also provides the means to program the ?ash memory. this could be initial programming of a blank device, erasure and re-programming of a previously programmed device, or programming of the ?ash memory by the application program in a running system. the boot loader code is executed every time the part is reset or powered up. the loader can either execute the isp command handler or the user application code, or, on the lpc134x, it can obtain the boot image as an attached msc device through usb. a low level during reset at the pio0_1 pin is considered an external hardware request to start the isp command handler or the usb device enumeration. the state of pio0_3 determines whether the uart or usb interface will be used (lpc134x only). caution if level three code read protection (crp3) is selected, no future factory testing can be performed on the device.
lpc1311_13_42_43_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 11 december 2009 26 of 53 nxp semiconductors lpc1311/13/42/43 32-bit arm cortex-m3 microcontroller 7.18.5 apb interface the apb peripherals are located on one apb bus. 7.18.6 ahb-lite the ahb-lite connects the instruction (i-code) and data (d-code) cpu buses of the arm cortex-m3 to the ?ash memory, the main static ram, and the boot rom. 7.18.7 external interrupt inputs all gpio pins can be level or edge sensitive interrupt inputs. 7.18.8 memory mapping control the cortex-m3 incorporates a mechanism that allows remapping the interrupt vector table to alternate locations in the memory map. this is controlled via the vector table offset register contained in the nvic. the vector table may be located anywhere within the bottom 1 gb of cortex-m3 address space. the vector table must be located on a 128 word (512 byte) boundary because the nvic on the lpc1311/13/42/43 is con?gured for 128 total interrupts. 7.19 emulation and debugging debug functions are integrated into the arm cortex-m3. serial wire debug is supported.
lpc1311_13_42_43_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 11 december 2009 27 of 53 nxp semiconductors lpc1311/13/42/43 32-bit arm cortex-m3 microcontroller 8. limiting values [1] the following applies to the limiting values: a) this product includes circuitry speci?cally designed for the protection of its internal devices from the damaging effects of excessive static charge. nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maximum. b) parameters are valid over operating temperature range unless otherwise speci?ed. all voltages are with respect to v ss unless otherwise noted. [2] tie together v dd(3v3) and v dd(io) externally. if separate supplies are used for v dd(3v3) and v dd(io) , ensure that the voltage difference between both supplies is smaller than or equal to 0.5 v. [3] including voltage on outputs in 3-state mode. [4] the peak current is limited to 25 times the corresponding maximum current. [5] dependent on package type. [6] human body model: equivalent to discharging a 100 pf capacitor through a 1.5 k w series resistor. table 6. limiting values in accordance with the absolute maximum rating system (iec 60134). [1] symbol parameter conditions min max unit v dd(3v3) supply voltage (3.3 v) core and external rail [2] 2.0 3.6 v v dd(io) input/output supply voltage [2] 2.0 3.6 v v i input voltage 5 v tolerant i/o pins; only valid when the v dd(io) supply voltage is present [3] - 0.5 +5.5 v i dd supply current per supply pin [4] - 100 ma i ss ground current per ground pin [4] - 100 ma i latch i/o latch-up current - (0.5v dd(io) ) < v i < (1.5v dd(io) ); t j < 125 c - 100 ma t stg storage temperature [5] - 65 +150 c t j(max) maximum junction temperature - 150 c p tot(pack) total power dissipation (per package) based on package heat transfer, not device power consumption - 1.5 w v esd electrostatic discharge voltage human body model; all pins [6] - 5000 +5000 v
lpc1311_13_42_43_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 11 december 2009 28 of 53 nxp semiconductors lpc1311/13/42/43 32-bit arm cortex-m3 microcontroller 9. static characteristics table 7. static characteristics t amb = - 40 c to +85 c, unless otherwise speci?ed. symbol parameter conditions min typ [1] max unit v dd(3v3) supply voltage (3.3 v) [2] 2.0 3.3 3.6 v v dd(io) input/output supply voltage [2] 2.0 3.3 3.6 v i dd supply current active mode; v dd(3v3) = 3.3 v; t amb =25 c; code while(1){} executed from ?ash; system clock = 12 mhz [3] [4] [5] -4-ma system clock = 72 mhz [4] [5] [6] -17-ma sleep mode; v dd(3v3) = 3.3 v; t amb =25 c; system clock = 12 mhz [3] [4] [5] -2-ma deep-sleep mode; v dd(3v3) = 3.3 v; t amb =25 c [7] -30- m a deep power-down mode; v dd(3v3) = 3.3 v; v dd(io) = 3.3 v; t amb =25 c [8] - 220 - na i dd(io) i/o supply current deep power-down mode; v dd(3v3) = 3.3 v; v dd(io) = 3.3 v; t amb =25 c [8] [9] -20-na standard port pins and reset pin; see figure 16 , figure 17 , figure 18 and figure 19 i il low-level input current v i = 0 v; on-chip pull-up resistor disabled --3 m a i ih high-level input current v i =v dd(io) ; on-chip pull-down resistor disabled --3 m a i oz off-state output current v o =0v; v o =v dd(io) ; on-chip pull-up/down resistors disabled --3 m a v i input voltage pin con?gured to provide a digital function [10] [11] [12] 0 - 5.0 v v o output voltage output active 0 - v dd(io) v v ih high-level input voltage 2.0 - - v v il low-level input voltage - - 0.8 v v hys hysteresis voltage 0.4 - - v v oh high-level output voltage i oh = - 4 ma [13] v dd(io) - 0.4 --v v ol low-level output voltage i ol = 4 ma [13] - - 0.4 v i oh high-level output current v oh =v dd(io) - 0.4 v [13] - 4--ma i ol low-level output current v ol = 0.4 v [13] 4--ma
lpc1311_13_42_43_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 11 december 2009 29 of 53 nxp semiconductors lpc1311/13/42/43 32-bit arm cortex-m3 microcontroller i ohs high-level short-circuit output current v oh =0v [14] -- - 45 ma i ols low-level short-circuit output current v ol =v dd(io) [14] - - 50 ma i pd pull-down current v i = 5 v 10 50 150 m a i pu pull-up current v i =0v - 15 - 50 - 85 m a v dd(io) lpc1311_13_42_43_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 11 december 2009 30 of 53 nxp semiconductors lpc1311/13/42/43 32-bit arm cortex-m3 microcontroller [1] typical ratings are not guaranteed. the values listed are at room temperature (25 c), nominal supply voltages. [2] tie together v dd(3v3) and v dd(io) externally. if separate supplies are used for v dd(3v3) and v dd(io) , ensure that the voltage difference between both supplies is smaller than or equal to 0.5 v. [3] irc enabled; system oscillator disabled; system pll disabled. [4] bod disabled. [5] all peripherals disabled in the ahbclkctrl register. peripheral clocks to uart, ssp, trace clock, and systick timer disabled in the syscon block. [6] irc disabled; system oscillator enabled; system pll enabled. [7] all oscillators and analog blocks turned off in the pdsleepcfg register; pdsleepcfg = 0xffff ffff [8] wakeup pin pulled high externally. [9] for lpc134x: usb_dp and usb_dm pulled low externally. [10] including voltage on outputs in 3-state mode. [11] v dd(3v3) and v dd(io) supply voltages must be present. [12] 3-state outputs go into 3-state mode when v dd(io) is grounded. [13] accounts for 100 mv voltage drop in all supply lines. [14] allowed as long as the current limit does not exceed the maximum current allowed by the device. [15] to v ss . [16] includes external resistors of 33 w 1 % on usb_dp and usb_dm. usb pins (lpc1342/43 only) i oz off-state output current 0v lpc1311_13_42_43_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 11 december 2009 31 of 53 nxp semiconductors lpc1311/13/42/43 32-bit arm cortex-m3 microcontroller [1] the adc is monotonic, there are no missing codes. [2] the differential linearity error (e d ) is the difference between the actual step width and the ideal step width. see figure 8 . [3] the integral non-linearity (e l(adj) ) is the peak difference between the center of the steps of the actual and the ideal transfer curve after appropriate adjustment of gain and offset errors. see figure 8 . [4] the offset error (e o ) is the absolute difference between the straight line which ?ts the actual curve and the straight line which ?ts the ideal curve. see figure 8 . [5] the gain error (e g ) is the relative difference in percent between the straight line ?tting the actual transfer curve after removing offset error, and the straight line which ?ts the ideal transfer curve. see figure 8 . [6] the absolute error (e t ) is the maximum difference between the center of the steps of the actual transfer curve of the non-calibrated adc and the ideal transfer curve. see figure 8 . table 8. adc static characteristics t amb = - 40 c to +85 c unless otherwise speci?ed; adc frequency 4.5 mhz, v dd(3v3) = 2.5 v to 3.6 v. symbol parameter conditions min typ max unit v ia analog input voltage 0 - v dd(3v3) v c ia analog input capacitance - - 1 pf e d differential linearity error [1] [2] -- 1 lsb e l(adj) integral non-linearity [3] -- 1.5 lsb e o offset error [4] -- 3.5 lsb e g gain error [5] - - 0.6 % e t absolute error [6] -- 4 lsb
lpc1311_13_42_43_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 11 december 2009 32 of 53 nxp semiconductors lpc1311/13/42/43 32-bit arm cortex-m3 microcontroller (1) example of an actual transfer curve. (2) the ideal transfer curve. (3) differential linearity error (e d ). (4) integral non-linearity (e l(adj) ). (5) center of a step of the actual transfer curve. fig 8. adc characteristics 002aae787 1023 1022 1021 1020 1019 (2) (1) 1024 1018 1019 1020 1021 1022 1023 7 123456 7 6 5 4 3 2 1 0 1018 (5) (4) (3) 1 lsb (ideal) code out v dd(3v3) - v ss 1024 offset error e o gain error e g offset error e o v ia (lsb ideal ) 1 lsb =
lpc1311_13_42_43_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 11 december 2009 33 of 53 nxp semiconductors lpc1311/13/42/43 32-bit arm cortex-m3 microcontroller 9.1 bod static characteristics [1] interrupt levels are selected by writing the level value to the bod control register bodctrl, see lpc13xx user manual . 9.2 power consumption table 9. bod static characteristics [1] t amb =25 c. symbol parameter conditions min typ max unit v th threshold voltage interrupt level 0 assertion - 1.69 - v de-assertion - 1.84 - v interrupt level 1 assertion - 2.29 - v de-assertion - 2.44 - v interrupt level 2 assertion - 2.59 - v de-assertion - 2.74 - v interrupt level 3 assertion - 2.87 - v de-assertion - 2.98 - v reset level 0 assertion - 1.49 - v de-assertion - 1.64 - v conditions: t amb = 25 c; active mode entered executing code while(1){} from ?ash; v dd(3v3) = 3.3 v; internal pull-up resistors disabled; system oscillator and system pll enabled; irc, bod disabled; all peripherals disabled in the ahbclkctrl register (ahbclkctrl = 0x1f); all peripheral clocks disabled. fig 9. typical supply current versus regulator supply voltage v dd(3v3) in active mode v dd(3v3) (v) 2.0 3.6 3.2 2.8 2.4 002aae993 9 12 6 15 18 i dd (ma) 3 24 mhz 48 mhz 12 mhz 36 mhz 72 mhz
lpc1311_13_42_43_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 11 december 2009 34 of 53 nxp semiconductors lpc1311/13/42/43 32-bit arm cortex-m3 microcontroller conditions: active mode entered executing code while(1){} from ?ash; v dd(3v3) = 3.3 v; internal pull-up resistors disabled; system oscillator and system pll enabled; irc, bod disabled; all peripherals disabled in the ahbclkctrl register (ahbclkctrl = 0x1f); all peripheral clocks disabled. fig 10. typical supply current versus temperature in active mode conditions: v dd(3v3) = 3.3 v; sleep mode entered from ?ash; internal pull-up resistors disabled; system oscillator and system pll enabled; irc, bod disabled; all peripherals disabled in the ahbclkctrl register (ahbclkctrl = 0x1f); all peripheral clocks disabled. fig 11. typical supply current versus temperature in sleep mode 002aae994 temperature ( c) - 40 85 35 10 60 - 15 6 15 12 9 18 i dd (ma) 3 24 mhz 12 mhz 36 mhz 72 mhz 48 mhz 002aae995 temperature ( c) - 40 85 35 10 60 - 15 2 8 6 4 10 i dd (ma) 0 12 mhz 36 mhz 72 mhz 48 mhz 24 mhz
lpc1311_13_42_43_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 11 december 2009 35 of 53 nxp semiconductors lpc1311/13/42/43 32-bit arm cortex-m3 microcontroller conditions: bod disabled; all oscillators and analog blocks turned off in the pdsleepcfg register; pdsleepcfg = 0xffff ffff. fig 12. typical supply current versus temperature in deep-sleep mode (analog blocks disabled) fig 13. typical supply current versus temperature in deep power-down mode 002aae998 temperature ( c) - 40 85 35 10 60 - 15 20 60 40 80 i dd ( m a) 0 v dd(3v3) = 3.6 v 3.3 v 2.0 v 002aae996 temperature ( c) - 40 85 35 10 60 - 15 200 800 600 400 1000 i dd (na) 0 v dd(3v3) = 3.6 v 3.3 v 2.0 v
lpc1311_13_42_43_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 11 december 2009 36 of 53 nxp semiconductors lpc1311/13/42/43 32-bit arm cortex-m3 microcontroller [1] typical ratings are not guaranteed. the values listed are at room temperature (25 c), nominal supply voltages. [2] all other blocks disabled in the pdsleepcfg register. 9.3 electrical pin characteristics table 10. power consumption in deep-sleep mode for individual analog blocks t amb = 25 c; v dd(3v3) = 3.3 v. analog block enabled in pdsleepcfg register conditions typical i dd [1] usb pll [2] 39 m a system pll [2] 39 m a system oscillator [2] 197 m a bod [2] 74 m a irc [2] 36 m a irc output [2] 27 m a conditions: v dd(3v3) = v dd(io) = 3.3 v; on pin pio0_7. fig 14. high-drive output: typical high-level output voltage v oh versus high-level output current i oh . i oh (ma) 0 60 40 20 10 50 30 002aae990 2.8 2.4 3.2 3.6 v oh (v) 2 t = 85 c 25 c - 40 c
lpc1311_13_42_43_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 11 december 2009 37 of 53 nxp semiconductors lpc1311/13/42/43 32-bit arm cortex-m3 microcontroller conditions: v dd(3v3) = v dd(io) = 3.3 v; on pins pio0_4 and pio0_5. fig 15. i 2 c-bus pins (high current sink): typical low-level output current i ol versus low-level output voltage v ol conditions: v dd(3v3) = v dd(io) = 3.3 v; standard port pins and pio0_7. fig 16. typical low-level output current i ol versus low-level output voltage v ol v ol (v) 0 0.6 0.4 0.2 002aaf019 20 40 60 i ol (ma) 0 t = 85 c 25 c - 40 c v ol (v) 0 0.6 0.4 0.2 002aae991 5 10 15 i ol (ma) 0 t = 85 c 25 c - 40 c
lpc1311_13_42_43_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 11 december 2009 38 of 53 nxp semiconductors lpc1311/13/42/43 32-bit arm cortex-m3 microcontroller conditions: v dd(3v3) = v dd(io) = 3.3 v; standard port pins. fig 17. typical high-level output voltage v oh versus high-level output source current i oh conditions: v dd(3v3) = v dd(io) = 3.3 v; standard port pins. fig 18. typical pull-up current i pu versus input voltage v i i oh (ma) 0 24 16 8 002aae992 2.8 2.4 3.2 3.6 v oh (v) 2 t = 85 c 25 c - 40 c v i (v) 0 5 4 23 1 002aae988 - 30 - 50 - 10 10 i pu ( m a) - 70 t = 85 c 25 c - 40 c
lpc1311_13_42_43_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 11 december 2009 39 of 53 nxp semiconductors lpc1311/13/42/43 32-bit arm cortex-m3 microcontroller conditions: v dd(3v3) = v dd(io) = 3.3 v; standard port pins. fig 19. typical pull-down current i pd versus input voltage v i v i (v) 0 5 4 23 1 002aae989 40 20 60 80 i pd ( m a) 0 t = 85 c 25 c - 40 c
lpc1311_13_42_43_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 11 december 2009 40 of 53 nxp semiconductors lpc1311/13/42/43 32-bit arm cortex-m3 microcontroller 10. dynamic characteristics 10.1 flash memory [1] number of program/erase cycles. 10.2 external clock [1] parameters are valid over operating temperature range unless otherwise speci?ed. [2] typical ratings are not guaranteed. the values listed are at room temperature (25 c), nominal supply voltages. table 11. flash characteristics t amb = - 40 c to +85 c, unless otherwise speci?ed. symbol parameter conditions min typ max unit n endu endurance [1] 10000 - - cycles t ret retention time powered 10 - - years unpowered 20 - - years table 12. dynamic characteristic: external clock t amb = - 40 c to +85 c; v dd(3v3) over speci?ed ranges. [1] symbol parameter conditions min typ [2] max unit f osc oscillator frequency 1 - 25 mhz t cy(clk) clock cycle time 40 - 1000 ns t chcx clock high time t cy(clk) 0.4 - - ns t clcx clock low time t cy(clk) 0.4 - - ns t clch clock rise time - - 5 ns t chcl clock fall time - - 5 ns fig 20. external clock timing (with an amplitude of at least v i(rms) = 200 mv) t chcl t clcx t chcx t cy(clk) t clch 002aaa907
lpc1311_13_42_43_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 11 december 2009 41 of 53 nxp semiconductors lpc1311/13/42/43 32-bit arm cortex-m3 microcontroller 10.3 internal oscillators [1] parameters are valid over operating temperature range unless otherwise speci?ed. [2] typical ratings are not guaranteed. the values listed are at room temperature (25 c), nominal supply voltages. 10.4 i 2 c-bus [1] parameters are valid over operating temperature range unless otherwise speci?ed. [2] main clock frequency 10 mhz; system clock divider ahbclkdiv = 0x1; i 2 c-bus interface con?gured in master mode. [3] bus capacitance c b = 550 pf; external pull-up resistance of 103 w . table 13. dynamic characteristic: internal oscillators t amb = - 40 c to +85 c; 2.7 v v dd(3v3) 3.6 v [1] . symbol parameter conditions min typ [2] max unit f osc(rc) internal rc oscillator frequency - 11.88 12 12.12 mhz conditions: frequency values are typical values. 12 mhz 1 % accuracy is guaranteed for 2.7 v v dd(3v3) 3.6 v and t amb = - 40 c to +85 c. variations between parts may cause the irc to fall outside the 12 mhz 1 % accuracy speci?cation for voltages below 2.7 v. fig 21. internal rc oscillator frequency f versus temperature temperature ( c) - 40 85 35 10 60 - 15 002aae987 11.95 12.05 12.15 f (mhz) 11.85 v dd(3v3) = 3.6 v 3.3 v 3.0 v 2.7 v 2.4 v 2.0 v table 14. dynamic characteristic: i 2 c-bus pins (fast-mode plus) t amb = - 40 c to +85 c; v dd(3v3) = v dd(io) = 3.3 v. [1] [2] [3] symbol parameter conditions min typ max unit f scl scl clock frequency - - 1 mhz t f fall time - - 45 ns t su;dat data set-up time 50 - - ns
lpc1311_13_42_43_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 11 december 2009 42 of 53 nxp semiconductors lpc1311/13/42/43 32-bit arm cortex-m3 microcontroller 10.5 ssp interface [1] t cy(clk) = (sspclkdiv (1 + scr) cpsdvsr) / f main . the clock cycle time derived from the spi bit rate t cy(clk) is a function of the main clock frequency f main , the ssp peripheral clock divider (sspclkdiv), the ssp scr parameter (speci?ed in the ssp0cr0 register), and the ssp cpsdvsr parameter (speci?ed in the ssp clock prescale register). [2] t amb = - 40 c to 85 c; v dd(3v3) = 2.0 v to 3.6 v; v dd(io) = 2.0 v to 3.6 v. [3] t cy(clk) = 12 t cy(pclk) . [4] t amb = 25 c; v dd(3v3) = 3.3 v; v dd(io) = 3.3 v. fig 22. i 2 c-bus pins clock timing p s 002aae860 t su;dat t f sda scl table 15. dynamic characteristics of ssp pins in spi mode symbol parameter conditions min max unit t cy(pclk) pclk cycle time 13.9 - ns t cy(clk) clock cycle time [1] 27.8 - ns ssp master t ds data set-up time in spi mode [2] 15 t cy(clk) ns t dh data hold time in spi mode [2] -0ns t v(q) data output valid time in spi mode [2] -10ns t h(q) data output hold time in spi mode [2] -0ns ssp slave t ds data set-up time in spi mode [3] [4] 0- ns t dh data hold time in spi mode [3] [4] 3 t cy(pclk) + 4 - ns t v(q) data output valid time in spi mode [3] [4] -3 t cy(pclk) + 11 ns t h(q) data output hold time in spi mode [3] [4] -2 t cy(pclk) + 5 ns
lpc1311_13_42_43_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 11 december 2009 43 of 53 nxp semiconductors lpc1311/13/42/43 32-bit arm cortex-m3 microcontroller fig 23. ssp master timing in spi mode sck (cpol = 0) mosi miso t cy(clk) t clk(h) t clk(l) t ds t dh t v(q) data valid data valid t h(q) sck (cpol = 1) data valid data valid mosi miso t ds t dh data valid data valid t h(q) data valid data valid t v(q) cpha = 1 cpha = 0 002aae829
lpc1311_13_42_43_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 11 december 2009 44 of 53 nxp semiconductors lpc1311/13/42/43 32-bit arm cortex-m3 microcontroller fig 24. ssp slave timing in spi mode sck (cpol = 0) mosi miso t cy(clk) t clk(h) t clk(l) t ds t dh t v(q) data valid data valid t h(q) sck (cpol = 1) data valid data valid mosi miso t ds t dh t v(q) data valid data valid t h(q) data valid data valid cpha = 1 cpha = 0 002aae830
lpc1311_13_42_43_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 11 december 2009 45 of 53 nxp semiconductors lpc1311/13/42/43 32-bit arm cortex-m3 microcontroller 10.6 usb interface (lpc1342/43 only) [1] characterized but not implemented as production test. guaranteed by design. table 16. dynamic characteristics: usb pins (full-speed) c l = 50 pf; r pu = 1.5 k w on d+ to v dd(3v3) , unless otherwise speci?ed. symbol parameter conditions min typ max unit t r rise time 10 % to 90 % 8.5 - 13.8 ns t f fall time 10 % to 90 % 7.7 - 13.7 ns t frfm differential rise and fall time matching t r /t f - - 109 % v crs output signal crossover voltage 1.3 - 2.0 v t feopt source se0 interval of eop see figure 25 160 - 175 ns t fdeop source jitter for differential transition to se0 transition see figure 25 - 2 - +5 ns t jr1 receiver jitter to next transition - 18.5 - +18.5 ns t jr2 receiver jitter for paired transitions 10 % to 90 % - 9 - +9 ns t eopr1 eop width at receiver must reject as eop; see figure 25 [1] 40 --ns t eopr2 eop width at receiver must accept as eop; see figure 25 [1] 82 --ns fig 25. differential data-to-eop transition skew and eop width 002aab561 t period differential data lines crossover point source eop width: t feopt receiver eop width: t eopr1 , t eopr2 crossover point extended differential data to se0/eop skew n t period + t fdeop
lpc1311_13_42_43_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 11 december 2009 46 of 53 nxp semiconductors lpc1311/13/42/43 32-bit arm cortex-m3 microcontroller 11. application information 11.1 suggested usb interface solutions (lpc1342/43 only) 11.2 xtal input the input voltage to the on-chip oscillators is limited to 1.8 v. if the oscillator is driven by a clock in slave mode, it is recommended that the input be coupled through a capacitor with c i = 100 pf. to limit the input voltage to the speci?ed range, choose an additional capacitor to ground c g which attenuates the input voltage by a factor c i /(c i +c g ). in slave mode, a minimum of 200 mv(rms) is needed. fig 26. lpc1342/43 usb interface on a self-powered device lpc134x usb-b connector usb_dp usb_connect soft-connect switch usb_dm usb_vbus v ssio v dd(io) r1 1.5 k w r s = 33 w 002aae608 r s = 33 w fig 27. lpc1342/43 usb interface on a bus-powered device lpc134x v dd(io) r1 1.5 k w 002aae609 usb-b connector usb_dp usb_dm usb_vbus v ssio r s = 33 w r s = 33 w
lpc1311_13_42_43_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 11 december 2009 47 of 53 nxp semiconductors lpc1311/13/42/43 32-bit arm cortex-m3 microcontroller 11.3 xtal printed-circuit board (pcb) layout guidelines the crystal should be connected on the pcb as close as possible to the oscillator input and output pins of the chip. take care that the load capacitors c x1 ,c x2 , and c x3 in case of third overtone crystal usage have a common ground plane. the external components must also be connected to the ground plain. loops must be made as small as possible in order to keep the noise coupled in via the pcb as small as possible. also parasitics should stay as small as possible. values of c x1 and c x2 should be chosen smaller accordingly to the increase in parasitics of the pcb layout. 11.4 standard i/o pad con?guration figure 29 shows the possible pin modes for standard i/o pins. the pull-up and pull-down resistors (r pu and r pd ) can be enabled or disabled. the default value for each standard port pin is input with r pu enabled. for details on pin modes and hysteresis control, see the lpc13xx user manual . fig 28. slave mode operation of the on-chip oscillator lpc1xxx xtalin c i 100 pf c g 002aae788 fig 29. standard i/o pad con?guration pin v dd(io) v ss r pd r pu enable output input 002aae828 hysteresis control
lpc1311_13_42_43_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 11 december 2009 48 of 53 nxp semiconductors lpc1311/13/42/43 32-bit arm cortex-m3 microcontroller 12. package outline fig 30. package outline sot313-2 (lqfp48) unit a max. a 1 a 2 a 3 b p ce (1) eh e ll p z y w v q references outline version european projection issue date iec jedec jeita mm 1.6 0.20 0.05 1.45 1.35 0.25 0.27 0.17 0.18 0.12 7.1 6.9 0.5 9.15 8.85 0.95 0.55 7 0 o o 0.12 0.1 0.2 1 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.75 0.45 sot313-2 ms-026 136e05 00-01-19 03-02-25 d (1) (1) (1) 7.1 6.9 h d 9.15 8.85 e z 0.95 0.55 d b p e e b 12 d h b p e h v m b d z d a z e e v m a 1 48 37 36 25 24 13 q a 1 a l p detail x l (a ) 3 a 2 x y c w m w m 0 2.5 5 mm scale pin 1 index lqfp48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm sot313-2
lpc1311_13_42_43_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 11 december 2009 49 of 53 nxp semiconductors lpc1311/13/42/43 32-bit arm cortex-m3 microcontroller fig 31. package outline (hvqfn33) references outline version european projection issue date iec jedec jeita - - - hvqfn33_po 09-03-17 09-03-23 unit mm max nom min 1.00 0.85 0.80 0.05 0.02 0.00 0.2 7.1 7.0 6.9 4.85 4.70 4.55 7.1 7.0 6.9 0.65 4.55 0.75 0.60 0.45 0.1 a (1) dimensions note 1. plastic or metal protrusions of 0.075 mm maximum per side are not included. hvqfn33: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 7 x 7 x 0.85 mm a 1 b 0.35 0.28 0.23 cd (1) d h e (1) e h 4.85 4.70 4.55 ee 1 e 2 4.55 lv 0.1 w 0.05 y 0.08 y 1 0 2.5 5 mm scale terminal 1 index area b a d e c y c y 1 x detail x a 1 a c b e 2 e 1 e e a c b v c w terminal 1 index area d h e h l 9 16 32 33 25 17 24 8 1
lpc1311_13_42_43_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 11 december 2009 50 of 53 nxp semiconductors lpc1311/13/42/43 32-bit arm cortex-m3 microcontroller 13. abbreviations table 17. abbreviations acronym description a/d analog-to-digital adc analog-to-digital converter ahb advanced high-performance bus amba advanced microcontroller bus architecture apb advanced peripheral bus bod brownout detection eop end of packet etm embedded trace macrocell fifo first-in, first-out gpio general purpose input/output i/o input/output lsb least signi?cant bit msc mass storage class phy physical layer pll phase-locked loop se0 single ended zero spi serial peripheral interface ssi serial synchronous interface ssp synchronous serial port sof start-of-frame tcm tightly-coupled memory ttl transistor-transistor logic uart universal asynchronous receiver/transmitter usb universal serial bus
lpc1311_13_42_43_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 11 december 2009 51 of 53 nxp semiconductors lpc1311/13/42/43 32-bit arm cortex-m3 microcontroller 14. revision history table 18. revision history document id release date data sheet status change notice supersedes lpc1311_13_42_43_1 20091211 product data sheet - -
lpc1311_13_42_43_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 11 december 2009 52 of 53 nxp semiconductors lpc1311/13/42/43 32-bit arm cortex-m3 microcontroller 15. legal information 15.1 data sheet status [1] please consult the most recently issued document before initiating or completing a design. [2] the term short data sheet is explained in section de?nitions. [3] the product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple dev ices. the latest product status information is available on the internet at url http://www .nxp .com . 15.2 de?nitions draft the document is a draft version only. the content is still under internal review and subject to formal approval, which may result in modi?cations or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. short data sheet a short data sheet is an extract from a full data sheet with the same product type number(s) and title. a short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. for detailed and full information see the relevant full data sheet, which is available on request via the local nxp semiconductors sales of?ce. in case of any inconsistency or con?ict with the short data sheet, the full data sheet shall prevail. 15.3 disclaimers general information in this document is believed to be accurate and reliable. however, nxp semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. right to make changes nxp semiconductors reserves the right to make changes to information published in this document, including without limitation speci?cations and product descriptions, at any time and without notice. this document supersedes and replaces all information supplied prior to the publication hereof. suitability for use nxp semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an nxp semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. nxp semiconductors accepts no liability for inclusion and/or use of nxp semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customers own risk. applications applications that are described herein for any of these products are for illustrative purposes only. nxp semiconductors makes no representation or warranty that such applications will be suitable for the speci?ed use without further testing or modi?cation. limiting values stress above one or more limiting values (as de?ned in the absolute maximum ratings system of iec 60134) may cause permanent damage to the device. limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the characteristics sections of this document is not implied. exposure to limiting values for extended periods may affect device reliability. terms and conditions of sale nxp semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www .nxp .com/pro? le/ter ms , including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by nxp semiconductors. in case of any inconsistency or con?ict between information in this document and such terms and conditions, the latter will prevail. no offer to sell or license nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. export control this document as well as the item(s) described herein may be subject to export control regulations. export might require a prior authorization from national authorities. 15.4 trademarks notice: all referenced brands, product names, service names and trademarks are the property of their respective owners. i 2 c-bus logo is a trademark of nxp b.v. 16. contact information for more information, please visit: http://www .nxp.com for sales of?ce addresses, please send an email to: salesad dresses@nxp.com document status [1] [2] product status [3] de?nition objective [short] data sheet development this document contains data from the objective speci?cation for product development. preliminary [short] data sheet quali?cation this document contains data from the preliminary speci?cation. product [short] data sheet production this document contains the product speci?cation.
nxp semiconductors lpc1311/13/42/43 32-bit arm cortex-m3 microcontroller ? nxp b.v. 2009. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com date of release: 11 december 2009 document identifier: lpc1311_13_42_43_1 please be aware that important notices concerning this document and the product(s) described herein, have been included in section legal information. 17. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4 ordering information . . . . . . . . . . . . . . . . . . . . . 3 4.1 ordering options . . . . . . . . . . . . . . . . . . . . . . . . 3 5 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6 pinning information . . . . . . . . . . . . . . . . . . . . . . 5 6.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 6.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 8 7 functional description . . . . . . . . . . . . . . . . . . 14 7.1 architectural overview. . . . . . . . . . . . . . . . . . . 14 7.2 arm cortex-m3 processor . . . . . . . . . . . . . . . 14 7.3 on-chip ?ash program memory . . . . . . . . . . . 15 7.4 on-chip sram . . . . . . . . . . . . . . . . . . . . . . . . 15 7.5 memory map. . . . . . . . . . . . . . . . . . . . . . . . . . 15 7.6 nested vectored interrupt controller (nvic). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 7.6.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 7.6.2 interrupt sources. . . . . . . . . . . . . . . . . . . . . . . 17 7.7 ioconfig block. . . . . . . . . . . . . . . . . . . . . . . 17 7.8 fast general purpose parallel i/o . . . . . . . . . . 17 7.8.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 7.9 usb interface (lpc1342/43 only). . . . . . . . . . 18 7.9.1 full-speed usb device controller . . . . . . . . . . 18 7.9.1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 7.10 uart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 7.10.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 7.11 ssp serial i/o controller . . . . . . . . . . . . . . . . . 19 7.11.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 7.12 i 2 c-bus serial i/o controller . . . . . . . . . . . . . . 19 7.12.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 7.13 10-bit adc . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 7.13.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 7.14 general purpose external event counters/timers . . . . . . . . . . . . . . . . . . . . . . . . 20 7.14.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 7.15 system tick timer . . . . . . . . . . . . . . . . . . . . . . 21 7.16 watchdog timer. . . . . . . . . . . . . . . . . . . . . . . . 21 7.16.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7.17 clocking and power control. . . . . . . . . . . . . . . 21 7.17.1 crystal oscillators . . . . . . . . . . . . . . . . . . . . . . 21 7.17.1.1 internal rc oscillator . . . . . . . . . . . . . . . . . . . 22 7.17.1.2 system oscillator. . . . . . . . . . . . . . . . . . . . . . . 23 7.17.2 system pll and usb pll . . . . . . . . . . . . . . . 23 7.17.3 clock output . . . . . . . . . . . . . . . . . . . . . . . . . . 23 7.17.4 wake-up process . . . . . . . . . . . . . . . . . . . . . . 23 7.17.5 power control . . . . . . . . . . . . . . . . . . . . . . . . . 23 7.17.5.1 sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7.17.5.2 deep-sleep mode. . . . . . . . . . . . . . . . . . . . . . 24 7.17.5.3 deep power-down mode . . . . . . . . . . . . . . . . 24 7.18 system control . . . . . . . . . . . . . . . . . . . . . . . . 24 7.18.1 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7.18.2 brownout detection . . . . . . . . . . . . . . . . . . . . 25 7.18.3 code security (code read protection - crp). . . . . . . . . . . . 25 7.18.4 boot loader. . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7.18.5 apb interface . . . . . . . . . . . . . . . . . . . . . . . . . 26 7.18.6 ahb-lite . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7.18.7 external interrupt inputs . . . . . . . . . . . . . . . . . 26 7.18.8 memory mapping control . . . . . . . . . . . . . . . . 26 7.19 emulation and debugging. . . . . . . . . . . . . . . . 26 8 limiting values . . . . . . . . . . . . . . . . . . . . . . . . 27 9 static characteristics . . . . . . . . . . . . . . . . . . . 28 9.1 bod static characteristics . . . . . . . . . . . . . . . 33 9.2 power consumption . . . . . . . . . . . . . . . . . . . . 33 9.3 electrical pin characteristics. . . . . . . . . . . . . . 36 10 dynamic characteristics . . . . . . . . . . . . . . . . . 40 10.1 flash memory . . . . . . . . . . . . . . . . . . . . . . . . 40 10.2 external clock. . . . . . . . . . . . . . . . . . . . . . . . . 40 10.3 internal oscillators . . . . . . . . . . . . . . . . . . . . . 41 10.4 i 2 c-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 10.5 ssp interface . . . . . . . . . . . . . . . . . . . . . . . . . 42 10.6 usb interface (lpc1342/43 only) . . . . . . . . . 45 11 application information . . . . . . . . . . . . . . . . . 46 11.1 suggested usb interface solutions (lpc1342/43 only) . . . . . . . . . . . . . . . . . . . . . 46 11.2 xtal input . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 11.3 xtal printed-circuit board (pcb) layout guidelines . . . . . . . . . . . . . . . . . 47 11.4 standard i/o pad con?guration . . . . . . . . . . . 47 12 package outline . . . . . . . . . . . . . . . . . . . . . . . . 48 13 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 50 14 revision history . . . . . . . . . . . . . . . . . . . . . . . 51 15 legal information . . . . . . . . . . . . . . . . . . . . . . 52 15.1 data sheet status . . . . . . . . . . . . . . . . . . . . . . 52 15.2 de?nitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 15.3 disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 52 15.4 trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 52 16 contact information . . . . . . . . . . . . . . . . . . . . 52 17 contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

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